307013-003 Datasheet, PDF (683/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
Bit
Description
Active State Link PM Control (APMC) — R/W. This bit indicates whether the root
port should enter L0s or L1 or both.
Bits
Definition
1:0
00b
Disabled
01b
L0s Entry is Enabled
10b
L1 Entry is Enabled
11b
L0s and L1 Entry Enabled
18.1.29 LSTS—Link Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 52h–53h
Default Value: See bit description
Attribute:
Size:
RO
16 bits
Bit
Description
15:14 Reserved
Data Link Layer Active (DLLA) — RO. D
13 ^{0 = Data Link Control and Management State Machine is not in the DL_Active state.}
(Default)
1 = Data Link Control and Management State Machine is in the DL_Active state.
12
Slot Clock Configuration (SCC) — RO. Set to 1b to indicate that the Intel^® ICH7 uses
the same reference clock as on the platform and does not generate its own clock.
Link Training (LT) — RO.
11 _{0 = Link training completed. (Default)}
1 = Link training is occurring.
10 Link Training Error (LTE) — RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW) — RO. This field indicates the negotiated width of the
given PCI Express* link. The contents of this NLW field is undefined if the link has not
successfully trained.
Port #
Possible Values
1
000001b, 000010b, 000100b
9:4
2
000001b
3
000001b
4
000001b
5
000001b, 000010b
6
000001b
NOTE: 000001b = x1 link width, 000010b =x2 linkwidth (not supported),
000100 = x4 linkwidth
Link Speed (LS) — RO. This field indicates the negotiated Link speed of the given PCI
3:0 Express* link.
01h = Link is 2.5 Gb/s.
Intel ^® ICH7 Family Datasheet
683