307013-003 Datasheet, PDF (584/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
14.1.2
DID—Device Identification Register (SMBUS—D31:F3)
Address:
02h–03h
Default Value: See bit description
Attribute:
Size:
RO
16 bits
14.1.3
Bit
15:0
Description
Device ID — RO. This is a 16-bit value assigned to the Intel^® ICH7 SMBus controller.
Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification Update for the
value of the Device ID Register.
PCICMD—PCI Command Register (SMBUS—D31:F3)
Address:
04h–05h
Default Value: 0000h
Attributes:
Size:
RO, R/W
16 bits
Bit
Description
15:11 Reserved
Interrupt Disable — R/W.
10 _{0 = Enable}
1 = Disables SMBus to assert its PIRQB# signal.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
8 0 = Enables SERR# generation.
1 = Disables SERR# generation.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — R/W.
6 _{0 = Disable}
1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2 Bus Master Enable (BME) — RO. Hardwired to 0.
1 Memory Space Enable (MSE) — RO. Hardwired to 0.
I/O Space Enable (IOSE) — R/W.
0 ^{0 = Disable}
1 = Enables access to the SM Bus I/O space registers as defined by the Base Address
Register.
584
Intel ^® ICH7 Family Datasheet