307013-003 Datasheet, PDF (744/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.22 CORBST—CORB Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Dh
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
7:1 Reserved.
CORB Memory Error Indication (CMEI) — R/WC.
0 = Error Not detected.
1 = The controller has detected an error in the path way between the controller and
memory. This may be an ECC bit error or any other type of detectable data error
0
which renders the command data fetched invalid.
NOTE: Software can clear this bit by writing a 1 to it. However, this type of error leaves
the audio subsystem in an un-viable state and typically requires a controller
reset by writing a 0 to the Controller Reset # bit (HDBAR + 08h: bit 0).
19.2.23 CORBSIZE—CORB Size Register
Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Eh
Default Value: 42h
Attribute:
Size:
RO
8 bits
Bit
Description
7:4
CORB Size Capability — RO. Hardwired to 0100b indicating that the ICH7 only supports
a CORB size of 256 CORB entries (1024B).
3:2 Reserved.
1:0 CORB Size — RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B).
19.2.24 RIRBLBASE—RIRB Lower Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 50h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:7
6:0
RIRB Lower Base Address — R/W. This field is the lower address of the Response
Input Ring Buffer, allowing the RIRB base address to be assigned on any 128-B
boundary. This register field must not be written when the DMA engine is running or the
DMA transfer may be corrupted.
RIRB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the RIRB to
be allocated with 128-B granularity to allow for cache line fetch optimizations.
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Intel ^® ICH7 Family Datasheet