307013-003 Datasheet, PDF (294/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.51
Bit
Description
Interrupt B Pin Route (IBR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTB# pin reported for device 27 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
3h = PIRQD#
6:4 4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
3
Reserved
Interrupt A Pin Route (IAR) — R/W. This field indicates which physical pin on the
ICH7 is connected to the INTA# pin reported for device 27 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
3h = PIRQD#
2:0 4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
NOTE: PIRQA#–PIRQD# are not on Ultra Mobile. Eventhough the register defaults to
a non-ICH7U pin routing, BIOS default sets the register for PIRQE#–PIRQH#.
OIC—Other Interrupt Control Register
Offset Address: 31FF–31FFh
Default Value: 00h
Attribute:
Size:
R/W
8-bit
Bit
Description
7:2 Reserved
Coprocessor Error Enable (CEN) — R/W.
1
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel^® ICH7 generates IRQ13 internally and holds it until an
I/O port F0h write. It will also drive IGNNE# active.
APIC Enable (AEN) — R/W.
0
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
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Intel ^® ICH7 Family Datasheet