307013-003 Datasheet, PDF (704/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.64 ULD — Upstream Link Description Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 190h–193h
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24 Target Port Number (PN) — RO. This field indicates the port number of the RCRB.
23:16
Target Component ID (TCID) — RO. This field returns the value of the ESD.CID field
(Chipset Configuration Space: Offset 0104h:bits 23:16) of the chip configuration
section, that is programmed by platform BIOS, since the root port is in the same
component as the RCRB.
15:2 Reserved.
1 Link Type (LT) — RO. This bit indicates that the link points to the Intel^® ICH7 RCRB.
0 Link Valid (LV) — RO. This bit indicates that this link entry is valid.
18.1.65 ULBA — Upstream Link Base Address Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 198h–19Fh
Default Value: See Description
Attribute:
Size:
RO
64 bits
Bit
Description
63:32 Base Address Upper (BAU) — RO. The RCRB of the Intel^® ICH7 is in 32-bit space.
31:0
Base Address Lower (BAL) — RO. This field matches the RCBA register
(D31:F0:Offset F0h) value in the LPC bridge.
18.1.66 PEETM — PCI Express Extended Test Mode Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 318h
Default Value: See Description
Attribute:
Size:
RO
8 bits
Bit
Description
7:3 Reserved
Scrambler Bypass Mode (BAU) — R/W.
0 = Normal operation. Scrambler and descrambler are used.
1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in
2
the receive direction.
NOTE: This functionality intended for debug/testing only.
NOTE: If bypassing scrambler with Intel^® ICH7 root port 1 in x4 configuration, each
ICH7 root port must have this bit set.
1:0 Reserved
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Intel ^® ICH7 Family Datasheet