307013-003 Datasheet, PDF (200/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.18.7
Issues Related to 64-Bit Timers with 32-Bit Processors
A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit
instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.
A race condition comes up if a 32-bit processor reads the 64-bit register using two
separate 32-bit reads. The danger is that just after reading one half, the other half rolls
over and changes the first half.
If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before
reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not
want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the
TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper
32-bits are always 0.
5.19
USB UHCI Host Controllers (D29:F0, F1, F2, and
F3)
The ICH7 contains four USB 2.0 full/low-speed host controllers that support the
standard Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host
Controller (UHC) includes a root hub with two separate USB ports each, for a total of
eight USB ports.
• Overcurrent detection on all eight USB ports is supported. The overcurrent inputs
are not 5 V tolerant, and can be used as GPIs if not needed.
• The ICH7’s UHCI host controllers are arbitrated differently than standard PCI
devices to improve arbitration latency.
• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows
support for USB full-speed signaling rates, instead of USB I/O buffers.
5.19.1
Data Structures in Main Memory
Section 3.1 - 3.3 of the Universal Host Controller Interface Specification, Revision 1.1
details the data structures used to communicate control, status, and data between
software and the ICH7.
5.19.2
Data Transfers to/from Main Memory
Section 3.4 of the Universal Host Controller Interface Specification, Revision 1.1
describes the details on how HCD and the ICH7 communicate via the Schedule data
structures.
5.19.3
Data Encoding and Bit Stuffing
The ICH7 USB employs NRZI data encoding (Non-Return to Zero Inverted) when
transmitting packets. Full details on this implementation are given in the Universal
Serial Bus Specification, Revision 2.0.
5.19.4 Bus Protocol
5.19.4.1
Bit Ordering
Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb,
through to the most significant bit (MSb) last.
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Intel ^® ICH7 Family Datasheet