307013-003 Datasheet, PDF (620/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Note:
16.1.1
Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers
except the following BIOS programmed registers as BIOS may not be invoked following
the D3-to-D0 transition. All resume well registers will not be reset by the D3_HOT to D0
transition.
Core well registers not reset by the D3_HOT to D0 transition:
• offset 2Ch–2Dh – Subsystem Vendor ID (SVID)
• offset 2Eh–2Fh – Subsystem ID (SID)
• offset 40h – Programmable Codec ID (PCID)
• offset 41h – Configuration (CFG)
Resume well registers will not be reset by the D3_HOT to D0 transition:
• offset 54h–55h – Power Management Control and Status (PCS)
• Bus Mastering Register: Global Status Register, bits 17:16
• Bus Mastering Register: SDATA_IN MAP register, bits 7:3
VID—Vendor Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
00h–01h
8086h
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
16.1.2
Bit
Description
15:0 Vendor ID. This is a 16-bit value assigned to Intel.
DID—Device Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
02h–03h
See bit description
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0
Description
Device ID — RO. This is a 16-bit value assigned to the Intel^® ICH7 AC ‘97 Audio
controller. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification Update
for the value of the Device ID Register.
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Intel ^® ICH7 Family Datasheet