307013-003 Datasheet, PDF (4/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

5.1.5 Peer Cycles .......................................................................................... 102
5.1.6 PCI-to-PCI Bridge Model ........................................................................ 102
5.1.7 IDSEL to Device Number Mapping ........................................................... 103
5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 103
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) (Desktop and Mobile Only) .......... 103
5.2.1 Interrupt Generation ............................................................................. 103
5.2.2 Power Management............................................................................... 104
5.2.2.1 S3/S4/S5 Support ................................................................... 104
5.2.2.2 Resuming from Suspended State ............................................... 104
5.2.2.3 Device Initiated PM_PME Message ............................................. 104
5.2.2.4 SMI/SCI Generation................................................................. 105
5.2.3 SERR# Generation ................................................................................ 105
5.2.4 Hot-Plug .............................................................................................. 106
5.2.4.1 Presence Detection .................................................................. 106
5.2.4.2 Message Generation ................................................................ 106
5.2.4.3 Attention Button Detection ....................................................... 107
5.2.4.4 SMI/SCI Generation................................................................. 107
5.3 LAN Controller (B1:D8:F0) (Desktop and Mobile Only) .......................................... 108
5.3.1 LAN Controller PCI Bus Interface............................................................. 108
5.3.1.1 Bus Slave Operation ................................................................ 109
5.3.1.2 CLKRUN# Signal (Mobile Only).................................................. 110
5.3.1.3 PCI Power Management ........................................................... 110
5.3.1.4 PCI Reset Signal...................................................................... 110
5.3.1.5 Wake-Up Events...................................................................... 111
5.3.1.6 Wake on LAN* (Preboot Wake-Up) ............................................. 112
5.3.2 Serial EEPROM Interface ........................................................................ 112
5.3.3 CSMA/CD Unit ...................................................................................... 113
5.3.3.1 Full Duplex ............................................................................. 113
5.3.3.2 Flow Control ........................................................................... 113
5.3.3.3 VLAN Support ......................................................................... 113
5.3.4 Media Management Interface ................................................................. 113
5.3.5 TCO Functionality ................................................................................. 114
5.3.5.1 Advanced TCO Mode ................................................................ 114
5.4 Alert Standard Format (ASF) (Desktop and Mobile Only) ....................................... 115
5.4.1 ASF Management Solution Features/Capabilities ....................................... 116
5.4.2 ASF Hardware Support .......................................................................... 117
5.4.2.1 Intel^® 82562EM/EX ................................................................. 117
5.4.2.2 EEPROM (256x16, 1 MHz) ........................................................ 117
5.4.2.3 Legacy Sensor SMBus Devices .................................................. 117
5.4.2.4 Remote Control SMBus Devices ................................................. 117
5.4.2.5 ASF Sensor SMBus Devices....................................................... 117
5.4.3 ASF Software Support ........................................................................... 118
5.5 LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 118
5.5.1 LPC Interface ....................................................................................... 118
5.5.1.1 LPC Cycle Types ...................................................................... 119
5.5.1.2 Start Field Definition ................................................................ 119
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ..................................... 120
5.5.1.4 SIZE...................................................................................... 120
5.5.1.5 SYNC..................................................................................... 121
5.5.1.6 SYNC Time-Out ....................................................................... 121
5.5.1.7 SYNC Error Indication .............................................................. 121
5.5.1.8 LFRAME# Usage...................................................................... 122
5.5.1.9 I/O Cycles .............................................................................. 122
5.5.1.10 Bus Master Cycles ................................................................... 122
5.5.1.11 LPC Power Management ........................................................... 122
5.5.1.12 Configuration and Intel^® ICH7 Implications................................. 123
5.5.2 SERR# Generation ................................................................................ 123
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Intel ^® ICH7 Family Datasheet