307013-003 Datasheet, PDF (743/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.20 CORBRP—CORB Read Pointer Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Ah
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15
14:8
7:0
CORB Read Pointer Reset — R/W. Software writes a 1 to this bit to reset the CORB
Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware
buffer within the Intel^® High Definition Audio controller. The hardware will physically
update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1
to verify that the reset completed correctly. Software must clear this bit back to 0 and
read back the 0 to verify that the clear completed correctly. The CORB DMA engine
must be stopped prior to resetting the Read Pointer or else DMA transfer may be
corrupted.
Reserved.
CORB Read Pointer (CORBRP) — RO. Software reads this field to determine how many
commands it can write to the CORB without over-running. The value read indicates the
CORB Read Pointer offset in DWord granularity. The offset entry read from this field has
been successfully fetched by the DMA controller and may be over-written by software.
Supports 256 CORB entries (256 x 4B=1KB). This field may be read while the DMA
engine is running.
19.2.21 CORBCTL—CORB Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 4Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved.
Enable CORB DMA Engine — R/W. After software writes a 0 to this bit, the hardware
may not stop immediately. The hardware will physically update the bit to 0 when the
DMA engine is truly stopped. Software must read a 0 from this bit to verify that the
1 _{DMA engine is truly stopped.}
0 = DMA stop
1 = DMA run
CORB Memory Error Interrupt Enable — R/W.
0 ^{0 = Disable.}
1 = Enable. The controller will generate an interrupt if the CMEI status bit (HDBAR +
4Dh: bit 0) is set.
Intel ^® ICH7 Family Datasheet
743