307013-003 Datasheet, PDF (183/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-40. Heartbeat Message Data (Sheet 2 of 2)
Field
Comment
SEQ[3:0]
System Power State
MESSAGE1
MESSAGE2
WDSTATUS
This is a sequence number. It initially is 0, and increments each time
the ICH7 sends a new message. Upon reaching 1111, the sequence
number rolls over to 0000. MSB (SEQ3) sent first.
00 = G0, 01 = G1, 10 = G2, 11 = Pre-Boot. MSB sent first
Will be the same as the MESSAGE1 Register. MSB sent first.
Will be the same as the MESSAGE2 Register. MSB sent first.
Will be the same as the WDSTATUS Register. MSB sent first.
5.16
Note:
5.16.1
IDE Controller (D31:F1)
The ICH7 IDE controller features one sets of interface signals that can be enabled, tri-
stated or driven low.
The IDE interfaces of the ICH7 can support several types of data transfers:
• Programmed I/O (PIO): Processor is in control of the data transfer.
• 8237 style DMA: DMA protocol that resembles the DMA on the ISA bus, although
it does not use the 8237 in the ICH7. This protocol off loads the processor from
moving data. This allows higher transfer rate of up to 16 MB/s.
• Ultra ATA/33: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 33 MB/s.
• Ultra ATA/66: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 66 MB/s.
• Ultra ATA/100: DMA protocol that redefines signals on the IDE cable to allow both
host and target throttling of data and transfer rates of up to 100 MB/s.
ICH7-U Ultra Mobile only supports one IDE device.
PIO Transfers
The ICH7 IDE controller includes both compatible and fast timing modes. The fast
timing modes can be enabled only for the IDE data ports. All other transactions to the
IDE registers are run in single transaction mode with compatible timings.
Up to two IDE devices may be attached to the IDE connector (drive 0 and drive 1); one
device (connector drive 0) on ICH7-U Ultra Mobile. The IDE_TIMP and IDE_TIMS
Registers permit different timing modes to be programmed for drive 0 and drive 1 of
the same connector.
The Ultra ATA/33/66/100 synchronous DMA timing modes can also be applied to each
drive by programming the IDE I/O Configuration register and the Synchronous DMA
Control and Timing registers. When a drive is enabled for synchronous DMA mode
operation, the DMA transfers are executed with the synchronous DMA timings. The PIO
transfers are executed using compatible timings or fast timings if also enabled.
Intel ^® ICH7 Family Datasheet
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