307013-003 Datasheet, PDF (412/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.6.2.2
RTC_REGB—Register B (General Configuration)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Bh
Attribute:
U0U00UUU (U: Undefined) Size:
No
Power Well:
R/W
8-bit
RTC
Bit
Description
Update Cycle Inhibit (SET) — R/W. Enables/Inhibits the update cycles. This bit is not
affected by RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update cycles will not occur until
7
SET is returned to 0. When set is one, the BIOS may initialize time and calendar
bytes safely.
NOTE: This bit should be set then cleared early in BIOS POST after each powerup
directly after coin-cell battery insertion.
Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on
any other reset.
6 _{0 = Disable.}
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register
A.
Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any
other reset.
5
0 = Disable.
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the
update cycle. An alarm can occur once a second, one an hour, once a day, or one a
month.
Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but
not on any other reset.
4
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
Square Wave Enable (SQWE) — R/W. This bit serves no function in the Intel^® ICH7.
3 It is left in this register bank to provide compatibility with the Motorola 146818B. The
ICH7 has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.
412
Intel ^® ICH7 Family Datasheet