307013-003 Datasheet, PDF (248/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.25.4.3
Note:
Multiple Page Write Usage Model
The system BIOS and Intel^® Active Management Technology firmware usage models
require that the serial flash device support multiple writes (minimum of 512 writes) to
a page (256 bytes) without requiring a preceding erase command. BIOS commonly
uses capabilities such as counters that are typically implemented by using byte writes
to ‘increment’ the bits within a page that have been designated as the counter. The
Intel AMT firmware usage model requires the capability for multiple data updates within
any given page. These data updates occur via byte writes without executing a
preceding erase to the given page. Both the BIOS and Intel AMT firmware multiple
page write usage models apply to sequential and non-sequential data writes.
This usage model requirement is based on any given bit only being written once from a
‘1’ to a ‘0’ without requiring the preceding erase. An erase would be required to change
bits back to the ‘1’ state.
5.25.5
Flash Protection
There are three types of Flash Protection mechanisms:
1. BIOS Range Write Protection
2. SMI#-Based Global Write Protection
3. Shared Flash Address Range Protection
The three mechanisms are conceptually OR’d together such that if any of the
mechanisms indicate that the access should be blocked, then it is blocked. Table 5-64
provides a summary of the Three Mechanisms.
Table 5-64. Flash Protection Mechanism Summary
Mechanism
Accesses
Blocked
BIOS Range
Write
Protection
Writes
Write Protect Writes
BIOS BAR
Reads and
Writes
Range Reset-Override
Specific
or SMI#-
Equivalent Function on FWH
?
Override?
Yes
Reset Override FWH Sector Protection
Same as Write Protect in
No
SMI# Override previous ICH components for
FWH
Yes
Reset Override
Not Applicable- Specific to
Flash Sharing
A blocked command will appear to software to finish, except that the Blocked Access
status bit is set in this case.
5.25.5.1
BIOS Range Write Protection
The ICH7 provides a method for blocking writes to specific ranges in the SPI flash when
the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) and the address of the
requested command against the base and limit fields of a Write Protected BIOS range.
Note:
Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
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Intel ^® ICH7 Family Datasheet