307013-003 Datasheet, PDF (164/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-31. Causes of Wake Events
Cause
RTC Alarm
Power Button
States Can
Wake From¹
How Enabled
S1–S5² Set RTC_EN bit in PM1_EN register
S1–S5
Always enabled as Wake event
GPE0_EN register
GPI[0:15]
Classic USB
LAN
(Desktop and
Mobile only)
RI#
AC ‘97 / Intel^®
High Definition
Audio
Primary PME#
Secondary PME#
PCI_EXP_WAKE#
(Desktop and
Mobile only)
PCI_EXP PME
Message
(Desktop and
Mobile only)
SMBALERT#
SMBus Slave
Message
SMBus Host
Notify message
received
S1–S5²
S1–S5
S1–S5
S1–S5²
S1–S5²
S1–S5
S1–S5
S1–S5
NOTE: GPIs that are in the core well are not capable of waking
the system from sleep states where the core well is not
powered.
Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in
GPE0_EN register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN register
Set AC97_EN bit in GPE0_EN register
PME_B0_EN bit in GPE0_EN register
Set PME_EN bit in GPE0_EN register.
PCI_EXP_WAKE bit³
S1
S1–S5
S1–S5
S1–S5
Must use the PCI Express* WAKE# pin rather than messages
for wake from S3,S4, or S5.
Always enabled as Wake event
Wake/SMI# command always enabled as a Wake event.
Note: SMBus Slave Message can wake the system from S1–
S5, as well as from S5 due to Power Button Override.
HOST_NOTIFY_WKEN bit SMBus Slave Command register.
Reported in the SMB_WAK_STS bit in the GPEO_STS register.
NOTES:
1.
If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events
are due to Power Button, Hard Reset Without Cycling (See Command Type 3 in
Table 5-55), and Hard Reset System (See Command Type 4 in Table 5-55).
2.
This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and
SLP_TYP bits via software, or if there is a power failure.
3.
When the WAKE# pin is active and the PCI Express device is enabled to wake the system,
the ICH7 will wake the platform.
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Intel ^® ICH7 Family Datasheet