307013-003 Datasheet, PDF (559/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
13.1.28 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F7)
Address Offset: 70h–73h
Attribute:
R/W, R/WC
Default Value: 00000000h
Size:
32 bits
Power Well:
Suspend
NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit
Description
31:30 Reserved — RO. Hardwired to 00h
29:22
SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
1 = Bits 29:22 correspond to the Port Owner bits for ports 1 (22) through 8 (29). These
bits are set to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to
0.
SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.
21 ^{0 = Power State bits Not modified.}
1 = Software modified the Power State bits in the Power Management Control/Status
(PMCSR) register (D29:F7:54h).
SMI on Async — R/WC. Software clears these bits by writing a 1 to it.
20 _{0 = No Async Schedule Enable bit change}
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
SMI on Periodic — R/WC. Software clears this bit by writing a 1 it.
19 _{0 = No Periodic Schedule Enable bit change.}
1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.
SMI on CF — R/WC. Software clears this bit by writing a 1 it.
18 0 = No Configure Flag (CF) change.
1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.
SMI on HCHalted — R/WC. Software clears this bit by writing a 1 it.
17 _{0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being cleared).}
1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).
SMI on HCReset — R/WC. Software clears this bit by writing a 1 it.
16 _{0 = HCRESET did Not transitioned to 1.}
1 = HCRESET transitioned to 1.
15:14 Reserved — RO. Hardwired to 00h
13:6
SMI on PortOwner Enable — R/W.
0 = Disable.
1 = Enable. When any of these bits are 1 and the corresponding SMI on PortOwner bits
are 1, then the host controller will issue an SMI. Unused ports should have their
corresponding bits cleared.
SMI on PMSCR Enable — R/W.
5
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller will issue
an SMI.
SMI on Async Enable — R/W.
4
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will issue
an SMI
Intel ^® ICH7 Family Datasheet
559