307013-003 Datasheet, PDF (806/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 2 of 2)
Sym
1
Parameter
Mode 0
(ns)
Min Max
Mode 1
(ns)
Min Max
Mode 2
(ns)
Min Max
Measuring
Location
Figure
CRC word valid hold time at
t92b
sender (from DMACK#
negation until CRC may
become invalid) (see Note ²)
6.2
—
6.2
—
6.2
—
Host
Connector
(Tcvh)
STROBE output released-to-
t93 driving to the first transition of 0
critical timing (Tzfs)
—
0
—
0
—
Device
Connector
23-12
Data Output Released-to-
t94 Driving Until the First Tunisian 70
of Critical Timing (Tdzfs)
—
48
—
31
—
Sender
Connector
23-9
t95 Unlimited Interlock Time (Tui) 0
—
0
—
0
—
Host
Connector
23-9
t96a
Maximum time allowed for
output drivers to release
(from asserted or negated)
(Taz)
— 10 — 10 — 10 See Note 2
Minimum time for drivers to
t96b assert or negate (from
released) (Tzad)
0
—
0
—
0
—
Device
Connector
Ready-to-final-STROBE time
t97
(no STROBE edges shall be
sent this long after negation
of DMARDY#) (Trfs)
—
75
—
70
—
60
Sender
Connector
23-9
t98a
Maximum time before
releasing IORDY (Tiordyz)
— 20
20
20
Device
Connector
t98b
Minimum time before driving
IORDY (see Note ²) (Tziordy)
0
—
0
—
0
—
Device
Connector
Time from STROBE edge to
negation of DMARQ or
t99 assertion of STOP (when
sender terminates a burst)
(Tss)
50
—
50
—
50
—
Sender
Connector
23-11
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment – 6 with Packet Interface
(ATA/ATAPI – 6) specification name.
2. See the AT Attachment – 6 with Packet Interface (ATA/ATAPI – 6) specification for further details on
measuring these timing parameters.
806
Intel ^® ICH7 Family Datasheet