307013-003 Datasheet, PDF (6/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

5.11
5.12
5.13
5.14
5.10.4.2 Level-Triggered Operation......................................................... 142
5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 142
5.10.4.4 Interrupt Message Format ........................................................ 142
Serial Interrupt (D31:F0) .................................................................................. 143
5.11.1 Start Frame ......................................................................................... 143
5.11.2 Data Frames ........................................................................................ 144
5.11.3 Stop Frame .......................................................................................... 144
5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 144
5.11.5 Data Frame Format ............................................................................... 145
Real Time Clock (D31:F0) ................................................................................. 146
5.12.1 Update Cycles ...................................................................................... 146
5.12.2 Interrupts ............................................................................................ 147
5.12.3 Lockable RAM Ranges............................................................................ 147
5.12.4 Century Rollover ................................................................................... 147
5.12.5 Clearing Battery-Backed RTC RAM ........................................................... 147
Processor Interface (D31:F0) ............................................................................ 149
5.13.1 Processor Interface Signals .................................................................... 149
5.13.1.1 A20M# (Mask A20).................................................................. 149
5.13.1.2 INIT# (Initialization)................................................................ 150
5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric
Error) .................................................................................... 150
5.13.1.4 NMI (Non-Maskable Interrupt) .................................................. 151
5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) ........ 151
5.13.1.6 CPU Power Good (CPUPWRGOOD) ............................................. 151
5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) ...................... 151
5.13.2 Dual-Processor Issues (Desktop Only) ..................................................... 152
5.13.2.1 Signal Differences ................................................................... 152
5.13.2.2 Power Management ................................................................. 152
Power Management (D31:F0) ............................................................................ 153
5.14.1 Features .............................................................................................. 153
5.14.2 Intel^® ICH7 and System Power States ..................................................... 153
5.14.3 System Power Planes ............................................................................ 156
5.14.4 SMI#/SCI Generation ............................................................................ 156
5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) .............................. 159
5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ....................... 159
5.14.5 Dynamic Processor Clock Control ............................................................ 159
5.14.5.1 Transition Rules among S0/Cx and Throttling States..................... 160
5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) ................................. 161
5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) .................. 161
5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only) ............. 161
5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................ 161
5.14.6.1 Conditions for Checking the PCI Clock ........................................ 162
5.14.6.2 Conditions for Maintaining the PCI Clock..................................... 162
5.14.6.3 Conditions for Stopping the PCI Clock ........................................ 162
5.14.6.4 Conditions for Re-Starting the PCI Clock ..................................... 162
5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) ............ 162
5.14.7 Sleep States ........................................................................................ 163
5.14.7.1 Sleep State Overview............................................................... 163
5.14.7.2 Initiating Sleep State ............................................................... 163
5.14.7.3 Exiting Sleep States................................................................. 163
5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (
Desktop and Mobile only) ......................................................... 165
5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 165
5.14.8 Thermal Management............................................................................ 166
5.14.8.1 THRM# Signal......................................................................... 166
5.14.8.2 Processor Initiated Passive Cooling ............................................ 166
5.14.8.3 THRM# Override Software Bit ................................................... 167
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Intel ^® ICH7 Family Datasheet