307013-003 Datasheet, PDF (418/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8
Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicate, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
10.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)
Table 10-9 shows a small part of the configuration space for PCI Device 31: Function 0.
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
Table 10-9. Power Management PCI Register Address Map (PM—D31:F0)
Offset
Mnemonic
Register Name
Default
Type
A0h
A2h
A4h
A9h
AAh
ABh
ADh
B0h
B1h-B2h
B3h
B8–BBh
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
Cx-STATE_CNF
C4-TIMING_CNT
BM_BREAK_EN
MSC_FUN
EL_STS
EL_CNTL1
EL_CNTL2
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
Cx State Configuration (Mobile/Ultra
Mobile Only).
C4 Timing Control (Mobile/Ultra Mobile
Only).
BM_BREAK_EN
Miscellaneous Functionality
Intel^® Quick Resume Technology Status
Register (Digital Home Only)
Intel Quick Resume Technology Control 1
Register (Digital Home Only)
Intel Quick Resume Technology Control 2
Register (Digital Home Only)
GPI_ROUT
GPI Route Control
0000h
00h
00h
00h
R/W, RO,
R/WO
R/W, R/
WC
R/W, R/
WC
R/W
00h
R/W
00h
R/W
00h
R/W
00h
R/WC, RO
F000h
R/W, RO,
WO
00h
R/W, RO
0000000
0h
R/W
418
Intel ^® ICH7 Family Datasheet