307013-003 Datasheet, PDF (184/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.16.1.1
PIO IDE Timing Modes
IDE data port transaction latency consists of startup latency, cycle latency, and
shutdown latency. Startup latency is incurred when a PCI master cycle targeting the
IDE data port is decoded and the DA[2:0] and CSxx# lines are not set up. Startup
latency provides the setup time for the DA[2:0] and CSxx# lines prior to assertion of
the read and write strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time.
Recovery time is provided so that transactions may occur back-to-back on the IDE
interface (without incurring startup and shutdown latency) without violating minimum
cycle periods for the IDE interface. The command strobe assertion width for the
enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,
or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set
to 1, 2, 3, or 4 PCI clocks.
If IORDY is asserted when the initial sample point is reached, no wait-states are added
to the command strobe assertion length. If IORDY is negated when the initial sample
point is reached, additional wait-states are added. Since the rising edge of IORDY must
be synchronized, at least two additional PCI clocks are added.
Shutdown latency is incurred after outstanding scheduled IDE data port transactions
(either a non-empty write post buffer or an outstanding read prefetch cycles) have
completed and before other transactions can proceed. It provides hold time on the
DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and
DIOW#). Shutdown latency is two PCI clocks in duration.
The IDE timings for various transaction types are shown in Table 5-41.
Table 5-41. IDE Transaction Timings (PCI Clocks)
IDE Transaction Type
Startup
Latency
IORDY
Sample
Point (ISP)
Recovery Time
(RCT)
Shutdown
Latency
Non-Data Port Compatible
4
11
22
2
Data Port Compatible
3
6
14
2
Fast Timing Mode
2
2–5
1–4
2
5.16.1.2
IORDY Masking
The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point
(ISP) on a drive by drive basis via the IDETIM Register.
5.16.1.3
PIO 32-Bit IDE Data Port Accesses
A 32-bit PCI transaction run to the IDE data address (01F0h primary) results in two
back to back 16-bit transactions to the IDE data port. The 32-bit data port feature is
enabled for all timings, not just enhanced timing. For compatible timings, a shutdown
and startup latency is incurred between the two, 16-bit halves of the IDE transaction.
This ensures that the chip selects are deasserted for at least two PCI clocks between
the two cycles.
184
Intel ^® ICH7 Family Datasheet