307013-003 Datasheet, PDF (674/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.17 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 28h–2Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
31:0
Description
Prefetchable Memory Base Upper Portion (PMBU) — R/W. This field contains the
Upper 32-bits of the prefetchable address base.
18.1.18 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 2Ch–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. This field contains the
Upper 32-bits of the prefetchable address limit.
18.1.19 CAPP—Capabilities List Pointer Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 34h
Default Value: 40h
Attribute:
Size:
R0
8 bits
Bit
Description
7:0
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first
entry in the capabilities list is at 40h in configuration space.
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Intel ^® ICH7 Family Datasheet