307013-003 Datasheet, PDF (669/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.5
Bit
Description
Master Data Parity Error Detected (DPED) — R/WC.
8
0 = No data parity error received.
1 = Root port received a completion with a data parity error on the backbone and
PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.
7
Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base
Specification.
6 Reserved
5 66 MHz Capable — Reserved per the PCI Express* Base Specification.
4 Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status — RO. Indicates status of Hot-Plug and power management
interrupts on the root port that result in INTx# message generation.
3
0 = Interrupt is deasserted.
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the
state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5:04h:bit 10).
2:0 Reserved
RID—Revision Identification Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
18.1.6
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
PI—Programming Interface Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 09h
Default Value: 00h
Attribute:
Size:
RO
8 bits
18.1.7
Bit
Description
Programming Interface — RO.
7:0
00h = No specific register level programming interface defined.
SCC—Sub Class Code Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 0Ah
Default Value: 04h
Attribute:
Size:
RO
8 bits
Bit
Sub Class Code (SCC) — RO.
7:0
04h = PCI-to-PCI bridge.
Description
Intel ^® ICH7 Family Datasheet
669