307013-003 Datasheet, PDF (764/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

High Precision Event Timer Registers
20.1.6
Bit
Description
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set
to enable timer n to cause an interrupt when it times out.
2
0 = Enable.
1 = Disable (Default). The timer can still count and generate appropriate status bits,
but will not cause an interrupt.
Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.
0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is
generated. If another interrupt occurs, another edge will be generated.
1
1 = The timer interrupt is level triggered. This means that a level-triggered interrupt
is generated. The interrupt will be held active until it is cleared by writing to the
bit in the General Interrupt Status Register. If another interrupt occurs before the
interrupt is cleared, the interrupt will remain active.
0
Reserved. These bits will return 0 when read.
NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any
unimplemented registers will return an undetermined value.
TIMn_COMP—Timer n Comparator Value Register
Address Offset:
Attribute:
Default Value:
Timer 0:
Timer 1:
Timer 2:
R/W
N/A
108h–10Fh,
128h–12Fh,
148h–14Fh
Size:
64 bit
Bit
63:0
Description
Timer Compare Value — R/W. Reads to this register return the current value of the
comparator
Timers 0, 1, or 2 are configured to non-periodic mode:
Writes to this register load the value against which the main counter should be
compared for this timer.
• When the main counter equals the value last written to this register, the corresponding
interrupt can be generated (if so enabled).
• The value in this register does not change based on the interrupt being generated.
Timer 0 is configured to periodic mode:
• When the main counter equals the value last written to this register, the corresponding
interrupt can be generated (if so enabled).
• After the main counter equals the value in this register, the value in this register is increased
by the value last written to the register.
For example, if the value written to the register is 00000123h, then
1. An interrupt will be generated when the main counter reaches 00000123h.
2. The value in this register will then be adjusted by the hardware to 00000246h.
3. Another interrupt will be generated when the main counter reaches 00000246h
4. The value in this register will then be adjusted by the hardware to 00000369h
• As each periodic interrupt occurs, the value in this register will increment. When the
incremented value is greater than the maximum value possible for this register (FFFFFFFFh
for a 32-bit timer or FFFFFFFFFFFFFFFFh for a 64-bit timer), the value will wrap around
through 0. For example, if the current value in a 32-bit timer is FFFF0000h and the last value
written to this register is 20000, then after the next interrupt the value will change to
00010000h
Default value for each timer is all 1s for the bits that are implemented. For example,
a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a
default value of FFFFFFFFFFFFFFFFh.
§
764
Intel ^® ICH7 Family Datasheet