307013-003 Datasheet, PDF (514/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.37.3 STTT2 — SATA Indexed Registers Index 74h
(SATA TX Termination Test Register 2)
Address Offset: Index 74h – 77h
Attribute:
Default Value: 00000000h
Size:
.
Bit
Description
31:18 Reserved.
Port 3 TX Termination Test Enable — R/W:
0 = Port 3 TX termination port testing is disabled.
17 _{1 = Enables testing of Port 3 TX termination.}
NOTE: This bit only to be used for system board testing.
Port 2 TX Termination Test Enable — R/W:
0 = Port 2 TX termination port testing is disabled.
16 _{1 = Enables testing of Port 2 TX termination.}
NOTE: This bit only to be used for system board testing.
15:0 Reserved.
R/W
32 bits
12.1.38 SCAP0—SATA Capability Register 0 (SATA–D31:F2)
Address Offset: A8h–ABh
Default Value: 00100012h
Attribute:
Size:
RO
32 bits
This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.
Bit
Description
31:24
23:20
19:16
15:8
7:0
Reserved
Major Revision (MAJREV) — RO: Major revision number of the SATA Capability Pointer
implemented.
Minor Revision (MINREV) — RO: Minor revision number of the SATA Capability Pointer
implemented.
Next Capability Pointer (NEXT) — RO: Points to the next capability structure. 00h
indicates this is the last capability pointer.
Capability ID (CAP)— RO: This value of 12h has been assigned by the PCI SIG to
designate the SATA Capability Structure.
514
Intel ^® ICH7 Family Datasheet