307013-003 Datasheet, PDF (413/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.6.2.3
Bit
Description
Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation.
This bit is not affected by RSMRST# nor any other reset signal.
2
0 = BCD
1 = Binary
Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is
not affected by RSMRST# nor any other reset signal.
1 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and
PM as one.
1 = Twenty-four hour mode.
Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per
year. The days for the hour adjustment are those specified in United States federal law
as of 1987, which is different than previous years. This bit is not affected by RSMRST#
nor any other reset signal.
0 = Daylight Savings Time updates do not occur.
0 _{1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to}
3:00:00 AM.
b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it
is changed to 1:00:00 AM. The time must increment normally for at least two
update cycles (seconds) previous to these conditions for the time change to occur
properly.
RTC_REGC—Register C (Flag Register)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Ch
Attribute:
00U00000 (U: Undefined) Size:
No
Power Well:
Writes to Register C have no effect.
RO
8-bit
RTC
Bit
Description
Interrupt Request Flag (IRQF) — RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE).
7 This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST#
or a read of Register C.
Periodic Interrupt Flag (PF) — RO. This bit is cleared upon RSMRST# or a read of
Register C.
6 _{0 = If no taps are specified via the RS bits in Register A, this flag will not be set.}
1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is
1.
Alarm Flag (AF) — RO.
5 _{0 = This bit is cleared upon RTCRST# or a read of Register C.}
1 = Alarm Flag will be set after all Alarm values match the current time.
Update-Ended Flag (UF) — RO.
4 _{0 = The bit is cleared upon RSMRST# or a read of Register C.}
1 = Set immediately following an update cycle for each second.
3:0 Reserved. Will always report 0.
Intel ^® ICH7 Family Datasheet
413