307013-003 Datasheet, PDF (338/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.3.15
STA—Status Register
(ASF Controller—B1:D8:F0)
Offset Address: F2h
Default Value: 40h
Attribute:
Size:
R/W
8 bits
This register gives status indication about several aspects of ASF.
Bit
Description
7
EEPROM Loading (STA_LOAD) — R/W. EEPROM defaults are in the process of being
loaded when this bit is a 1.
EEPROM Invalid Checksum Indication (STA_ICRC) — R/W. This bit should be read
only after the EEC_LOAD bit is a 0.
6
0 = Valid
1 = Invalid checksum detected for ASF portion of the EEPROM.
5:4 Reserved
Power Cycle Status (STA_CYCLE) — R/W.
3 _{0 = Software clears this bit by writing a 1.}
1 = This bit is set when a Power Cycle operation has been issued.
Power Down Status (STA_DOWN) — R/W.
2 _{0 = Software clears this bit by writing a 1}
1 = This bit is set when a Power Down operation has been issued.
Power Up Status (STA_UP) — R/W.
1 0 = Software clears this bit by writing a 1
1 = This bit is set when a Power Up operation has been issued.
System Reset Status (STA_RST) — R/W.
0 _{0 = Software clears this bit by writing a 1}
1 = This bit is set when a System Reset operation has been issued.
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Intel ^® ICH7 Family Datasheet