307013-003 Datasheet, PDF (231/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
other words, if a Start –Address–Read occurs (which is invalid for SMBus Read or Write
protocol), and the address matches the ICH7’s Slave Address, the ICH7 will still grab
the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–
Read sequence beginning at bit 20. Once again, if the Address matches the ICH7’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and
proceed with the Slave Read cycle.
Note:
An external microcontroller must not attempt to access the ICH7’s SMBus Slave logic
until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).
5.21.7.3
Format of Host Notify Command
The ICH7 tracks and responds to the standard Host Notify command as specified in the
System Management Bus (SMBus) Specification, Version 2.0. The host address for this
command is fixed to 0001000b. If the ICH7 already has data for a previously-received
host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address
byte of the protocol. This allows the host to communicate non-acceptance to the
master and retain the host notify address and data values for the previous cycle until
host software completely services the interrupt.
Note:
Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 5-58 shows the Host Notify format.
Table 5-58. Host Notify Format
Bit
Description
1 Start
8:2
SMB Host Address — 7
bits
9 Write
10 ACK (or NACK)
Driven By
External
Master
External
Master
External
Master
Intel^® ICH7
17:11 Device Address – 7 bits
External
Master
18 Unused — Always 0
19 ACK
27:20 Data Byte Low — 8 bits
28 ACK
36:29 Data Byte High — 8 bits
37 ACK
38 Stop
External
Master
ICH7
External
Master
ICH7
External
Master
ICH7
External
Master
Comment
Always 0001_000
Always 0
ICH7 NACKs if HOST_NOTIFY_STS is 1
Indicates the address of the master;
loaded into the Notify Device Address
Register
7-bit-only address; this bit is inserted to
complete the byte
Loaded into the Notify Data Low Byte
Register
Loaded into the Notify Data High Byte
Register
Intel ^® ICH7 Family Datasheet
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