307013-003 Datasheet, PDF (356/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.20
Bit
Description
VGA Enable (VGAE) — R/W. When set to a 1, the ICH7 PCI bridge forwards the
following transactions to PCI regardless of the value of the I/O base and limit registers.
The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE
(D30:F0:04 bit 0) being set.
• Memory addresses: 000A0000h-000BFFFFh
3
• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address
must be 0, and bits [15:10] of the address are ignored (i.e., aliased).
The same holds true from secondary accesses to the primary interface in reverse. That
is, when the bit is 0, memory and I/O addresses on the secondary interface between
the above ranges will be claimed.
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the
2
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is
set, the ICH7 PCI bridge will block any forwarding from primary to secondary of I/O
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh).
SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface
SERR# assertions on the primary interface. When set, the PCI bridge will forward
1
SERR# pin.
• SERR# is asserted on the secondary interface.
• This bit is set.
• CMD.SEE (D30:F0:04 bit 8) is set.
Parity Error Response Enable (PERE) — R/W.
0
0 = Disable
1 = The ICH7 PCI bridge is enabled for parity error reporting based on parity errors on
the PCI bus.
SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)
Offset Address: 40h–41h
Default Value: 00h
Attribute:
Size:
R/W, RO
16 bits
This register allows software to hide the PCI devices, either plugged into slots or on the
motherboard.
Bit
15:8
7
6
5
4
3
Description
Reserved
Hide Device 7 (HD7) — R/W, RO. Same as bit 0 of this register, except for device 7
(AD[23])
Hide Device 6 (HD6) — R/W, RO. Same as bit 0 of this register, except for device 6
(AD[22])
Hide Device 5 (HD5) — R/W, RO. Same as bit 0 of this register, except for device 5
(AD[21])
Hide Device 4 (HD4) — R/W, RO. Same as bit 0 of this register, except for device 4
(AD[20])
Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3
(AD[19])
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Intel ^® ICH7 Family Datasheet