307013-003 Datasheet, PDF (702/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
Bit
Description
Bad TLP Mask (BT) — R/WO.
6 0 = No mask
1 = Mask for bad TLP reception.
5:1 Reserved
Receiver Error Mask (RE) — R/WO.
0 _{0 = No mask}
1 = Mask for receiver errors.
18.1.60 AECC — Advanced Error Capabilities and Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 158h–15Bh
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:9 Reserved
8 ECRC Check Enable (ECE) — RO. ECRC is not supported.
7 ECRC Check Capable (ECC) — RO. ECRC is not supported.
6 ECRC Generation Enable (EGE) — RO. ECRC is not supported.
5 ECRC Generation Capable (EGC) — RO. ECRC is not supported.
4:0 First Error Pointer (FEP) — RO.
18.1.61 RES — Root Error Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 170h–173h
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32 bits
Bit
Description
31:27
Advanced Error Interrupt Message Number (AEMN) — RO. There is only one error
interrupt allocated.
26:4
3
Reserved
Multiple ERR_FATAL/NONFATAL Received (MENR) — RO. For Intel^® ICH7, only
one error will be captured.
ERR_FATAL/NONFATAL Received (ENR) — R/WC.
2 0 = No error message received.
1 = Either a fatal or a non-fatal error message is received.
1 Multiple ERR_COR Received (MCR) — RO. For ICH7, only one error will be captured.
ERR_COR Received (CR) — R/WC.
0 _{0 = No error message received.}
1 = A correctable error message is received.
702
Intel ^® ICH7 Family Datasheet