307013-003 Datasheet, PDF (634/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Table 16-3. Native Audio Bus Master Control Registers (Sheet 2 of 2)
Offset
54h
55h
56h
58h
5Ah
Mnemonic
PI2_CIV
PI2_LVI
PI2_SR
PI2_PICB
PI2_PIV
Name
PCM In 2 Current Index Value
PCM In 2 Last Valid Index
PCM In 2 Status
PCM In 2 Position in Current Buffer
PCM In 2 Prefetched Index Value
Default
00h
00h
0001h
0000h
00h
5Bh
PI2_CR PCM In 2 Control
00h
60h
64h
65h
66h
68h
6Ah
SPBAR
SPCIV
SPLVI
SPSR
SPPICB
SPPIV
S/PDIF Buffer Descriptor List Base
Address
S/PDIF Current Index Value
S/PDIF Last Valid Index
S/PDIF Status
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
00000000h
00h
00h
0001h
0000h
00h
6Bh
SPCR
S/PDIF Control
00h
80h
SDM
SData_IN Map
00h
Access
RO
R/W
R/WC, RO
RO
RO
R/W, R/W
(special)
R/W
RO
R/W
R/WC, RO
RO
RO
R/W, R/W
(special)
R/W, RO
Note:
Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers
except the registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well
registers will not be reset by the D3_HOT to D0 transition.
Core well registers and bits not reset by the D3_HOT to D0 transition:
• offset 2Ch–2Fh – bits 6:0 Global Control (GLOB_CNT)
• offset 30h–33h – bits [29,15,11:10,0] Global Status (GLOB_STA)
• offset 34h – Codec Access Semaphore Register (CAS)
Resume well registers and bits will not be reset by the D3_HOT to D0 transition:
• offset 30h–33h – bits [17:16] Global Status (GLOB_STA)
634
Intel ^® ICH7 Family Datasheet