307013-003 Datasheet, PDF (425/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.1.5
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile/Ultra Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
AAh
00h
No
Core
Attribute:
Size:
Usage:
This register is used to enable C-state related modes.
R/W
8-bit
ACPI, Legacy
Bit
Description
7:4 Reserved
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the Intel^®
ICH7-M/ICH7-U waits for from the deassertion of DPRSLPVR to the deassertion of
STP_CPU#. This provides a programmable time for the processor’s voltage to stabilize
when exiting from a C4 state. This changes the value for t266.
3:2
Bits t266_min
00b
95 µs
01b
22 µs
10b
34 µs
11b
t266_max
101 µs
28 µs
40 µs
Comment
Default
Value used for “Fast” VRMs
Recommended Value
Reserved
DPSLP-TO-SLP — R/W. This field selects the DPSLP# deassertion to CPU_SLP#
deassertion time (t270). Normally this value is determined by the
CPU_PLL_LOCK_TIME field in the GEN_PMCON_2 register. When this field is non-zero,
then the values in this register have higher priority. It is software’s responsibility to
program these fields in a consistent manner.
1:0
Bits
t270
00b
Use value in CPU_PLL_LOCK_TIME field (default is 30 µs)
01b
20 µs
10b
15 µs (Recommended Value)
11b
10 µs
Intel ^® ICH7 Family Datasheet
425