307013-003 Datasheet, PDF (357/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.21
Bit
Description
2
Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2
(AD[18])
1
Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1
(AD[17])
Hide Device 0 (HD0) — R/W, RO.
0 = The PCI configuration cycles for this slot are not affected.
0
1 = Intel^® ICH7 hides device 0 on the PCI bus. This is done by masking the IDSEL
(keeping it low) for configuration cycles to that device. Since the device will not see
its IDSEL go active, it will not respond to PCI configuration cycles and the
processor will think the device is not present. AD[16] is used as IDSEL for device 0.
DTC—Delayed Transaction Control Register
(PCI-PCI—D30:F0)
Offset Address: 44h–47h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
Discard Delayed Transactions (DDT) — R/W.
0 = Logged delayed transactions are kept.
1 = The Intel^® ICH7 PCI bridge will discard any delayed transactions it has logged. This
includes transactions in the pending queue, and any transactions in the active
queue, whether in the hard or soft DT state. The prefetchers will be disabled and
31
return to an idle state.
NOTE: If a transaction is running on PCI at the time this bit is set, that transaction will
continue until either the PCI master disconnects (by de-asserting FRAME#) or
the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI
bridge when the delayed transaction queues are empty and have returned to an
idle state. Software sets this bit and polls for its completion
Block Delayed Transactions (BDT) — R/W.
0 = Delayed transactions accepted
30 _{1 = The ICH7 PCI bridge will not accept incoming transactions which will result in}
delayed transactions. It will blindly retry these cycles by asserting STOP#. All
postable cycles (memory writes) will still be accepted.
29: 8 Reserved
7: 6
Maximum Delayed Transactions (MDT) — R/W. This field controls the maximum
number of delayed transactions that the ICH7 PCI bridge will run. Encodings are:
00 =) 2 Active, 5 pending
01 =) 2 active, no pending
10 =) 1 active, no pending
11 =) Reserved
5 Reserved
Auto Flush After Disconnect Enable (AFADE) — R/W.
0 = The PCI bridge will retain any fetched data until required to discard by producer/
4
consumer rules.
1 = The PCI bridge will flush any prefetched data after either the PCI master (by de-
asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI
transfer.
Intel ^® ICH7 Family Datasheet
357