307013-003 Datasheet, PDF (415/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.7 Processor Interface Registers (LPC I/F—D31:F0)
Table 10-8 is the register address map for the processor interface registers.
Table 10-8. Processor Interface PCI Register Address Map (LPC I/F—D31:F0)
Offset Mnemonic
Register Name
Default
Type
61h
70h
92h
F0h
CF9h
NMI_SC
NMI_EN
PORT92
COPROC_ERR
RST_CNT
NMI Status and Control
NMI Enable
Fast A20 and Init
Coprocessor Error
Reset Control
00h
R/W, RO
80h
R/W (special)
00h
R/W
00h
R/W
00h
R/W
10.7.1
NMI_SC—NMI Status and Control Register
(LPC I/F—D31:F0)
I/O Address: 61h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W, RO
8-bit
Core
Bit
Description
SERR# NMI Source Status (SERR#_NMI_STS) — RO.
1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and
if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2
to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port
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61h, this bit must be 0.
NOTE: This bit is set by any of the Intel^® ICH7 internal sources of SERR; this includes
SERR assertions forwarded from the secondary PCI bus, errors on a PCI
Express* port, or other internal functions that generate SERR#.
IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.
1 = Bit is set if an LPC agent (via SERIRQ) asserted IOCHK# and if bit 3
6
(IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0.
To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h,
this bit must be a 0.
Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current
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state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI
reset for this bit to have a determinate value. When writing to port 61h, this bit must
be a 0.
Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or
4 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to
port 61h, this bit must be a 0.
IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.
3 _{0 = Enabled.}
1 = Disabled and cleared.
Intel ^® ICH7 Family Datasheet
415