307013-003 Datasheet, PDF (265/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
Table 7-1.
Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)
Offset
Mnemonic
Register Name
Default
Type
3410–3413h
GCS
General Control and Status
3414–3414h
BUC
Backed Up Control
3418–341Bh
341C–341Fh
FD
Function Disable
CG
Clock Gating (Mobile/Ultra
Mobile Only)
0000000xh
0000001xb
(Mobile/Ultra Mobile
Only)
0000000xb
(Desktop Only)
See bit description
00000000h
R/W,
R/WLO
R/W
R/W, RO
R/W, RO
7.1.1
7.1.2
VCH—Virtual Channel Capability Header Register
Offset Address: 0000–0003h
Default Value: 10010002h
Attribute:
Size:
RO
32-bit
Bit
31:20
19:16
15:0
Description
Next Capability Offset (NCO) — RO.This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates support as a version 1 capability
structure.
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability
item.
VCAP1—Virtual Channel Capability #1 Register
Offset Address: 0004–0007h
Default Value: 00000801h
Attribute:
Size:
RO
32-bit
Bit
31:12
11:10
9:8
7
6:4
3
2:0
Description
Reserved
Port Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the port
arbitration table is 4 bits (to allow up to 8 ports).
Reference Clock (RC) — RO. Fixed at 100 ns.
Reserved
Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there are no
additional VCs of low priority with extended capabilities.
Reserved
Extended VC Count (EVC) — RO. This field indicates that there is one additional VC
(VC1) that exists with extended capabilities.
Intel ^® ICH7 Family Datasheet
265