307013-003 Datasheet, PDF (393/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.3.1
TCW—Timer Control Word Register (LPC I/F—D31:F0)
I/O Address: 43h
Default Value: All bits undefined
Attribute:
Size:
WO
8 bits
This register is programmed prior to any counter being accessed to specify counter
modes. Following part reset, the control words for each register are undefined and each
counter output is 0. Each timer must be programmed to bring it into a known state.
Bit
Description
Counter Select — WO. The Counter Selection bits select the counter the control word
acts upon as shown below. The Read Back Command is selected when bits[7:6] are
both 1.
7:6 ^{00 = Counter 0 select}
01 = Counter 1 select
10 = Counter 2 select
11 = Read Back Command
Read/Write Select — WO. These bits are the read/write control bits. The actual
counter programming is done through the counter port (40h for counter 0, 41h for
counter 1, and 42h for counter 2).
5:4 ^{00 = Counter Latch Command}
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Counter Mode Selection — WO. These bits select one of six possible modes of
operation for the selected counter.
Bit Value
Mode
000b
Mode 0 Out signal on end of count (=0)
3:1
001b
Mode 1 Hardware retriggerable one-
shot
x10b
Mode 2 Rate generator (divide by n
counter)
x11b
Mode 3 Square wave output
100b
Mode 4 Software triggered strobe
101b
Mode 5 Hardware triggered strobe
Binary/BCD Countdown Select — WO.
0 0 = Binary countdown is used. The largest possible binary count is 216
1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104
There are two special commands that can be issued to the counters through this
register, the Read Back Command and the Counter Latch Command. When these
commands are chosen, several bits within this register are redefined. These register
formats are described below:
RDBK_CMD—Read Back Command (LPC I/F—D31:F0)
The Read Back Command is used to determine the count value, programmed mode,
and current states of the OUT pin and Null count flag of the selected counter or
counters. Status and/or count may be latched in any or all of the counters by selecting
the counter during the register write. The count and status remain latched until read,
and further latch commands are ignored until the count is read. Both count and status
of the selected counters may be latched simultaneously by setting both bit 5 and bit 4
Intel ^® ICH7 Family Datasheet
393