307013-003 Datasheet, PDF (520/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.2.1
BMIC[P,S]—Bus Master IDE Command Register (D31:F2)
Address Offset: Primary: BAR + 00h
Secondary: BAR + 08h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:4 Reserved. Returns 0.
Read / Write Control (R/WC) — R/W. This bit sets the direction of the bus master
transfer: This bit must NOT be changed when the bus master function is active.
3
0 = Memory reads
1 = Memory writes
2:1 Reserved. Returns 0.
Start/Stop Bus Master (START) — R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot
be stopped and then resumed. If this bit is reset while bus master operation is still
active (i.e., the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus
Master IDE Status register for that IDE channel is set) and the drive has not yet
finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for
that IDE channel is not set), the bus master command is said to be aborted and
data transferred from the drive may be discarded instead of being written to
system memory.
1 = Enables bus master operation of the controller. Bus master operation does not
0
actually start unless the Bus Master Enable bit (D31:F1:04h, bit 2) in PCI
configuration space is also set. Bus master operation begins when this bit is
detected changing from 0 to 1. The controller will transfer data between the IDE
device and memory only when this bit is set. Master operation can be halted by
writing a 0 to this bit.
NOTE: This bit is intended to be cleared by software after the data transfer is
completed, as indicated by either the Bus Master IDE Active bit being cleared or
the Interrupt bit of the Bus Master IDE Status register for that IDE channel
being set, or both. Hardware does not clear this bit automatically. If this bit is
cleared to 0 prior to the DMA data transfer being initiated by the drive in a
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Intel ^® ICH7 Family Datasheet