307013-003 Datasheet, PDF (347/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9.1.4
Note:
Bit
Description
Bus Master Enable (BME) — R/W.
2 0 = Disable
1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI.
Memory Space Enable (MSE) — R/W. Controls the response as a target for memory
cycles targeting PCI.
1
0 = Disable
1 = Enable
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles
targeting PCI.
0
0 = Disable
1 = Enable
PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06h–07h
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15
0 = Parity error Not detected.
1 = Indicates that the Intel^® ICH7 detected a parity error on the internal backbone.
This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set.
Intel ^® ICH7 Family Datasheet
347