307013-003 Datasheet, PDF (632/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
Table 16-2. Intel^® ICH7 Audio Mixer Register Configuration (Sheet 2 of 2)
Primary Offset Secondary Offset Tertiary Offset
(Codec ID =00) (Codec ID =01) (Codec ID =10)
5Ah
DAh
7Ch
FCh
7Eh
FEh
15Ah
17Ch
17Eh
NAMBAR Exposed Registers
(D30:F2)
Vendor Reserved
Vendor ID1
Vendor ID2
NOTE:
1.
Software should not try to access reserved registers
2.
Primary Codec ID cannot be changed. Secondary codec ID can be changed via bits 1:0 of
configuration register 40h. Tertiary codec ID can be changed via bits 3:2 of configuration
register 40h.
3.
The tertiary offset is only available through the memory space defined by the MMBAR
register.
The Bus Master registers are located from offset + 00h to offset + 51h and reside in the
AC ’97 controller. Accesses to these registers do not cause the cycle to be forwarded
over the AC-link to the codec. S/W could access these registers as bytes, word, DWord
or qword quantities, but reads must not cross DWord boundaries.
In the case of the split codec implementation, accesses to the different codecs are
differentiated by the controller by using address offsets 00h–7Fh for the primary codec,
address offsets 80h–FFh for the secondary codec and address offsets 100h–17Fh for the
tertiary codec.
The Global Control (GLOB_CNT) (D30:F2:2Ch) and Global Status (GLOB_STA)
(D30:F2:30h) registers are aliased to the same global registers in the audio and
modem I/O space. Therefore a read/write to these registers in either audio or modem
I/O space affects the same physical register.
Bus Mastering registers exist in I/O space and reside in the AC ’97 controller. The six
channels, PCM in, PCM in 2, PCM out, Mic in, Mic 2, and S/PDIF out, each have their
own set of Bus Mastering registers. The following register descriptions apply to all six
channels. The register definition section titles use a generic “x_” in front of the register
to indicate that the register applies to all six channels. The naming prefix convention
used in Table 16-3 and in the register description I/O address is as follows:
PI = PCM in channel
PO = PCM out channel
MC = Mic in channel
MC2 = Mic 2 channel
PI2 = PCM in 2 channel
SP = S/PDIF out channel.
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Intel ^® ICH7 Family Datasheet