307013-003 Datasheet, PDF (740/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.14 INTSTS—Interrupt Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 24h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in
31 ^{this register.}
NOTE: This bit is not affected by the D3_HOT to D0 transition.
Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.
0 = An interrupt condition did Not occur as described below.
1 = An interrupt condition occurred due to a Response Interrupt, a Response Buffer
Overrun Interrupt, or a SDIN State Change event. The exact cause can be
determined by interrogating other registers. This bit is an OR of all of the stated
30
interrupt status bits for this register.
29:8
NOTES:
1.
This bit is set regardless of the state of the corresponding interrupt enable bit,
but a hardware interrupt will not be generated unless the corresponding enable
bit is set.
2.
This bit is not affected by the D3_HOT to D0 transition.
Reserved
Stream Interrupt Status (SIS) — RO.
0 = An interrupt condition did Not occur on the corresponding stream.
1 = An interrupt condition occurred on the corresponding stream. This bit is an OR of all
of the stream’s interrupt status bits.
NOTE: These bits are set regardless of the state of the corresponding interrupt enable
bits.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
7:0
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
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Intel ^® ICH7 Family Datasheet