307013-003 Datasheet, PDF (72/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
2.20
Serial Peripheral Interface (SPI) (Desktop and
Mobile Only)
Table 2-20. Serial Peripheral Interface (SPI) Signals
Name
Type
Description
SPI_CS#
SPI_MISO
SPI_MOSI
SPI_ARB
SPI_CLK
I/O
SPI Chip Select: This chip select signal is also used as the SPI bus
request signal.
I
SPI Master IN Slave OUT: This signal is the data input pin for
Intel^® ICH7.
O
SPI Master OUT Slave IN: This signal is the data output pin for
ICH7.
SPI Arbitration: SPI_ARB is the SPI arbitration signal used to
I
arbitrate the SPI bus with Intel PRO 82573E Gigabit Ethernet
Controller when Shared Flash is implemented.
O
SPI Clock: This signal is the SPI clock signal. During idle, the bus
owner will drive the clock signal low. 17.86 MHz.
2.21
Intel^® Quick Resume Technology (Intel^® ICH7DH
Only)
2.22
Signal Name
EL_RSVD /
GPIO26
EL_STATE[1:0] /
GPIO[28:27]
Type
I/O
I/O
Description
Intel^® Quick Resume Technology Reserved: This signal is
reserved and should be left as a no connect when Intel Quick
Resume Technology is enabled.
NOTE: This signal cannot be reused as a GPIO when Intel Quick
Resume Technology is enabled.
Intel Quick Resume Technology State: Intel Quick Resume
Technology status signals that may optionally be used to drive front
chassis indicators. See Section 5.26.3 for details.
General Purpose I/O Signals
Table 2-21. General Purpose I/O Signals (Sheet 1 of 3)
Name^1,2
GPIO49
GPIO48
GPIO[47:40]
GPIO[39:38]
(Desktop and
Mobile Only)
GPIO37
(Desktop and
Mobile Only)
Type
I/O
I/O
N/A
Tolerance
V_CPU_IO
3.3 V
N/A
Power
Well
V_CPU_IO
Core
N/A
I/O
3.3 V
Core
I/O
3.3 V
Core
Default
Native
Native
N/A
GPI
GPI
Description
Multiplexed with CPUPWRGD
Multiplexed with GNT4#
Not implemented.
Unmultiplexed.
Multiplexed with SATA3GP.
72
Intel ^® ICH7 Family Datasheet