307013-003 Datasheet, PDF (741/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.15 WALCLK—Wall Clock Counter Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 30h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:0
Wall Clock Counter — RO. This 32-bit counter field is incremented on each link BCLK
period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0
with a period of approximately 179 seconds.
This counter is enabled while the BCLK bit is set to 1. Software uses this counter to
synchronize between multiple controllers. Will be reset on controller reset.
19.2.16 SSYNC—Stream Synchronization Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 34h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:8
7:0
Reserved
Stream Synchronization (SSYNC) — R/W.
0 = Data is Not blocked from being sent on or received from the link
1 = The set bits block data from being sent on or received from the link. Each bit
controls the associated stream descriptor (i.e., bit 0 corresponds to the first stream
descriptor, etc.)
To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits
for the associated stream descriptors are then set to 1 to start the DMA engines. When
all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at
the same time, and transmission or reception of bits to or from the link will begin
together at the start of the next full link frame.
To synchronously stop the streams, first these bits are set, and then the individual RUN
bits in the stream descriptor are cleared by software.
If synchronization is not desired, these bits may be left as 0, and the stream will simply
begin running normally when the stream’s RUN bit is set.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
Intel ^® ICH7 Family Datasheet
741