307013-003 Datasheet, PDF (161/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.5.2
5.14.5.3
5.14.5.4
5.14.6
Note:
Deferred C3/C4 (Mobile/Ultra Mobile Only)
Due to the new DMI protocol, if there is any bus master activity (other than true isoch),
then the C0-to-C3 transition will pause at the C2 state. ICH7 will keep the processor in
a C2 state until:
• ICH7 does not detect bus master activity.
• A break event occurs. In this case, the ICH7 will perform the C2 to C0 sequence.
Note that bus master traffic is not a break event in this case.
To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be
set. This will cause the BM_STS bit to read as 0 even if some bus master activity is
present. If this is not done, then the software may avoid even attempting to go to the
C3 or C4 state if it sees the BM_STS bit as 1.
If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH7 will treat bus master
activity as a break event. When reaching the C2 state, if there is any bus master
activity, the ICH7 will return the processor to a C0 state.
POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only)
When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH7 enables a mode of
operation where standard (non-isoch) bus master activity will not be treated as a full
break event from the C3 or C4 states. Instead, these will be treated merely as bus
master events and return the platform to a C2 state, and thus allow snoops to be
performed.
After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even
if the ARB_DIS bit is set.
POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only)
After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4)
is set, the platform can return to a C3 or C4 state (depending on where it was prior to
going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will
keep the processor in a C2 state until:
• Bus masters are no longer active.
• A break event occurs. Note that bus master traffic is not a break event in this case.
Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)
The PCI clock can be dynamically controlled independent of any other low-power state.
This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile
Design Guide, and is transparent to software.
The Dynamic PCI Clock control is handled using the following signals:
• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
• STP_PCI#: Used to stop the system PCI clock
The 33 MHz clock to the ICH7 is “free-running” and is not affected by the STP_PCI#
signal.
Intel ^® ICH7 Family Datasheet
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