307013-003 Datasheet, PDF (321/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
8.2.5
EEPROM_CNTL—EEPROM Control Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO, R/W, WO
8 bits
The EEPROM Control Register is a 16-bit field that enables a read from and a write to
the external EEPROM.
Bit
Description
7:4 Reserved
EEPROM Serial Data Out (EEDO) — RO. Note that this bit represents “Data Out”
3 from the perspective of the EEPROM device. This bit contains the value read from the
EEPROM when performing read operations.
EEPROM Serial Data In (EEDI) — WO. Note that this bit represents “Data In” from
2 the perspective of the EEPROM device. The value of this bit is written to the EEPROM
when performing write operations.
EEPROM Chip Select (EECS) — R/W.
1
0 = Drives the Intel^® ICH7’s EE_CS signal low to disable the EEPROM. this bit must be
set to 0 for a minimum of 1 μs between consecutive instruction cycles.
1 = Drives the ICH7’s EE_CS signal high, to enable the EEPROM.
EEPROM Serial Clock (EESK) — R/W. Toggling this bit clocks data into or out of the
EEPROM. Software must ensure that this bit is toggled at a rate that meets the EEPROM
0 ^{component’s minimum clock frequency specification.}
0 = Drives the ICH7’s EE_SHCLK signal low.
1 = Drives the ICH7’s EE_SHCLK signal high.
Intel ^® ICH7 Family Datasheet
321