307013-003 Datasheet, PDF (391/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.2.8
DMA Clear Byte Pointer Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Ch;
Ch. #4–7 = D8h
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
10.2.9
Bit
Description
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the
I/O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
7:0 Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
DMA Master Clear Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Ch. #0–3 = 0Dh;
Ch. #4–7 = DAh
xxxx xxxx
Attribute:
Size:
WO
8-bit
Bit
Description
Master Clear — WO. No specific pattern. Enabled with a write to the port. This has the
7:0 same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
10.2.10 DMA_CLMSK—DMA Clear Mask Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Ch. #0–3 = 0Eh;
Ch. #4–7 = DCh
xxxx xxxx
No
Attribute:
Size:
Power Well:
WO
8-bit
Core
Bit
Description
7:0
Clear Mask Register — WO. No specific pattern. Command enabled with a write to the
port.
Intel ^® ICH7 Family Datasheet
391