307013-003 Datasheet, PDF (447/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.12 SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 30h
00000000h
No
Core
Attribute:
Size:
Usage:
Note:
This register is symmetrical to the SMI status register.
R/W, R/W (special), WO
32 bit
ACPI or Legacy
Bit
31:26
25
24:19
18
17
16:15
14
13
12
11
10:8
Description
Reserved
Intel^® ICH7DH Only:
EL_SMI_EN — R/W.
0 = Disable
1 = Software sets this bit to enable Intel Quick Resume Technology logic to cause
SMI#
ICH7 and ICH7R and Mobile/Ultra Mobile Only:
Reserved
Reserved
INTEL_USB2_EN — R/W.
0 = Disable
1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.
LEGACY_USB2_EN — R/W.
0 = Disable
1 = Enables legacy USB2 logic to cause SMI#.
Reserved
PERIODIC_EN — R/W.
0 = Disable.
1 = Enables the Intel^® ICH7 to generate an SMI# when the PERIODIC_STS bit
(PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is
set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN
bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
Reserved
MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable.
1 = Enables ICH7 to trap accesses to the microcontroller range (62h or 66h) and
generate an SMI#. Note that “trapped’ cycles will be claimed by the ICH7 on
PCI, but not forwarded to LPC.
Reserved
Intel ^® ICH7 Family Datasheet
447