307013-003 Datasheet, PDF (156/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.3 System Power Planes
The system has several independent power planes, as described in Table 5-27. Note
that when a particular power plane is shut off, it should go to a 0 V level.
s
Table 5-27. System Power Plane
Plane
CPU
MAIN
MEMORY
DEVICE[n]
Controlled
By
Description
SLP_S3#
signal
SLP_S3#
signal
(S3_COLD)
or
SLP_S4#
signal
(S3_HOT)
SLP_S4#
signal
SLP_S5#
signal
GPIO
The SLP_S3# signal can be used to cut the power to the processor
completely. For mobile/Ultra Mobile systems, the DPRSLPVR
support allows lowering the processor’s voltage during the C4
state.
S3_HOT: The new S3_HOT state keeps more of the platform logic,
including the Intel^® ICH7 core well, powered to reduce the cost of
external power plane logic. SLP_S3# is only used to remove power
to the processor and to shut system clocks. This impacts the board
design, but there is no specific ICH7 bit or strap needed to indicate
which option is selected.
S3_COLD: When SLP_S3# goes active, power can be shut off to any
circuit not required to wake the system from the S3 state. Since
the S3 state requires that the memory context be preserved,
power must be retained to the main memory.
The processor, devices on the PCI bus, LPC I/F, and graphics will
typically be shut off when the Main power plane is shut, although
there may be small subsections powered.
S3_HOT: SLP_S4# is used to cut the main power well, rather than
using SLP_S3#. This impacts the board design, but there is no
specific ICH7 bit or strap needed to indicate which option is
selected.
When the SLP_S4# goes active, power can be shut off to any
circuit not required to wake the system from the S4. Since the
memory context does not need to be preserved in the S4 state,
the power to the memory can also be shut down.
When SLP_S5# goes active, power can be shut to any circuit not
required to wake the system from the S5 state. Since the memory
context does not need to be preserved in the S5 state, the power
to the memory can also be shut.
Individual subsystems may have their own power plane. For
example, GPIO signals may be used to control the power to disk
drives, audio amplifiers, or the display screen.
5.14.4
SMI#/SCI Generation
On any SMI# event taking place, ICH7 asserts SMI# to the processor, which causes it
to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is
set, SMI# goes inactive for a minimum of 4 PCICLK. If another SMI event occurs, SMI#
is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
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Intel ^® ICH7 Family Datasheet