307013-003 Datasheet, PDF (429/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.1.10 EL_CNT2—Intel^® Quick Resume Technology Control 2 Register (PM—
D31:F0) (ICH7DH Only)
Offset Address: B3h
Default Value: 00h
Power Well:
RTC
Attribute:
Size:
R/W, RO
8-bit
Bit
Description
7:1 Reserved
Intel Quick Resume Technology Enable (EL_EN)—R/W: This bit enables Intel
Quick Resume Technology.
0 = Disabled
1 = Enabled
0
When this bit is 0, the R/W bits of Intel Quick Resume Technology Control Registers
(EL_CNT1, EL_CNT2) scratchpad with no effect on hardware functions. Also, WO bits
have no effect on hardware functions.
BIOS software is expected to set this bit after booting. Default value for this bit is 0.
10.8.1.11 GPIO_ROUT—GPIO Routing Control Register
(PM—D31:F0)
Offset Address: B8h – BBh
Default Value: 00000000h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Note:
Bit
Description
31:30 GPIO15 Route — R/W. See bits 1:0 for description.
Same pattern for GPIO14 through GPIO3
5:4 GPIO2 Route — R/W. See bits 1:0 for description.
3:2 GPIO1 Route — R/W. See bits 1:0 for description.
GPIO0 Route — R/W. GPIO[15:0] can be routed to cause an SMI or SCI when the
GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event, even if the GPIO is NOT routed to cause an SMI# or SCI.
1:0 _{00 = No effect.}
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
GPIOs that are not implemented will not have the corresponding bits implemented in
this register.
Intel ^® ICH7 Family Datasheet
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