307013-003 Datasheet, PDF (687/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.33 RCTL—Root Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 5Ch–5Dh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
15:4
3
2
1
0
Description
Reserved
PME Interrupt Enable (PIE) — R/W.
0 = Interrupt generation disabled.
1 = Interrupt generation enabled when PCISTS.Interrupt Status (D28:F0/F1/F2/F3/F4/
F5:60h, bit 16) is in a set state (either due to a 0 to 1 transition, or due to this bit
being set with RSTS.IS already set).
System Error on Fatal Error Enable (SFE) — R/W.
0 = Disable. An SERR# will not be generated.
1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/
F5:04, bit 8) is set, if a fatal error is reported by any of the devices in the hierarchy
of this root port, including fatal errors in this root port.
System Error on Non-Fatal Error Enable (SNE) — R/W.
0 = Disable. An SERR# will not be generated.
1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/
F5:04, bit 8) is set, if a non-fatal error is reported by any of the devices in the
hierarchy of this root port, including non-fatal errors in this root port.
System Error on Correctable Error Enable (SCE) — R/W.
0 = Disable. An SERR# will not be generated.
1 = Enable. An SERR# will be generated, assuming CMD.SEE (D28:F0/F1/F2/F3/F4/
F5:04, bit 8) if a correctable error is reported by any of the devices in the hierarchy
of this root port, including correctable errors in this root port.
18.1.34 RSTS—Root Status Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 60h–63h
Default Value: 00000000h
Attribute:
Size:
R/WC, RO
32 bits
Bit
Description
31:18 Reserved
PME Pending (PP) — RO.
0 = Indicates no more PMEs are pending.
17 ^{1 = Indicates another PME is pending (this is implicit because of the definition of this bit}
being 1). Hardware will set the PME Status bit again and update the Requestor ID
appropriately. The PME pending bit is cleared by hardware if no more PMEs are
pending.
PME Status (PS) — R/WC.
16 ^{0 = PME was not asserted.}
1 = PME was asserted by the requestor ID in RID. Subsequent PMEs are kept pending
until this bit is cleared.
15:0
PME Requestor ID (RID) — RO. This field indicates the PCI requestor ID of the last
PME requestor. The value in this field is valid only when PS is set.
Intel ^® ICH7 Family Datasheet
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