307013-003 Datasheet, PDF (173/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.10.2 PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in Table 5-37.
Table 5-37. PIC Reserved Bits Return Values
PIC Reserved Bits
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
ICW4(0)
OCW2(4:3)
OCW3(7)
OCW3(5)
OCW3(4:3)
Value Returned
000
000
00
0
00
0
Reflects bit 6
01
5.14.10.3 Read Only Registers with Write Paths in ALT Access Mode
The registers described in Table 5-38 have write paths to them in ALT access mode.
Software restores these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
Table 5-38. Register Write Accesses in ALT Access Mode
I/O Address
Register Write Value
08h
D0h
DMA Status Register for channels 0–3.
DMA Status Register for channels 4–7.
5.14.11 System Power Supplies, Planes, and Signals
5.14.11.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#
The usage of SLP_S3# and SLP_S4# depends on whether the platform is configured for
S3_HOT and S3_COLD.
S3_HOT
The SLP_S3# output signal is used to cut power only to the processor and associated
subsystems and to optionally stop system clocks.
S3_COLD
The SLP_S3# output signal can be used to cut power to the system core supply, since it
only goes active for the STR state (typically mapped to ACPI S3). Power must be
maintained to the ICH7 resume well, and to any other circuits that need to generate
Wake signals from the STR state.
Intel ^® ICH7 Family Datasheet
173