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307013-003 Datasheet, PDF (19/848 Pages) Intel Corporation – Intel I/O Controller Hub 7 | |||
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13.2
13.1.19PWR_CNTL_STSâPower Management Control/
Status Register (USB EHCIâD29:F7) ...................................................... 553
13.1.20DEBUG_CAPIDâDebug Port Capability ID Register (USB EHCIâD29:F7) ...... 554
13.1.21NXT_PTR2âNext Item Pointer #2 Register (USB EHCIâD29:F7) ................ 554
13.1.22DEBUG_BASEâDebug Port Base Offset Register (USB EHCIâD29:F7) ......... 554
13.1.23USB_RELNUMâUSB Release Number Register (USB EHCIâD29:F7) ............ 555
13.1.24FL_ADJâFrame Length Adjustment Register (USB EHCIâD29:F7) .............. 555
13.1.25PWAKE_CAPâPort Wake Capability Register (USB EHCIâD29:F7) ............... 556
13.1.26LEG_EXT_CAPâUSB EHCI Legacy Support Extended
Capability Register (USB EHCIâD29:F7).................................................. 556
13.1.27LEG_EXT_CSâUSB EHCI Legacy Support Extended
Control / Status Register (USB EHCIâD29:F7) ......................................... 557
13.1.28SPECIAL_SMIâIntel Specific USB 2.0 SMI Register (USB EHCIâD29:F7) ..... 559
13.1.29ACCESS_CNTLâAccess Control Register (USB EHCIâD29:F7) .................... 560
Memory-Mapped I/O Registers .......................................................................... 561
13.2.1 Host Controller Capability Registers ........................................................ 561
13.2.1.1 CAPLENGTHâCapability Registers Length Register....................... 561
13.2.1.2 HCIVERSIONâHost Controller Interface Version Number
Register................................................................................. 562
13.2.1.3 HCSPARAMSâHost Controller Structural Parameters .................... 562
13.2.1.4 HCCPARAMSâHost Controller Capability Parameters Register........ 563
13.2.2 Host Controller Operational Registers ...................................................... 564
13.2.2.1 USB2.0_CMDâUSB 2.0 Command Register ................................ 565
13.2.2.2 USB2.0_STSâUSB 2.0 Status Register ...................................... 568
13.2.2.3 USB2.0_INTRâUSB 2.0 Interrupt Enable Register ....................... 570
13.2.2.4 FRINDEXâFrame Index Register ............................................... 571
13.2.2.5 CTRLDSSEGMENTâControl Data Structure Segment Register ........ 572
13.2.2.6 PERIODICLISTBASEâPeriodic Frame List Base Address Register .... 572
13.2.2.7 ASYNCLISTADDRâCurrent Asynchronous List Address Register ..... 573
13.2.2.8 CONFIGFLAGâConfigure Flag Register ....................................... 573
13.2.2.9 PORTSCâPort N Status and Control Register .............................. 573
13.2.3 USB 2.0-Based Debug Port Register ........................................................ 577
13.2.3.1 CNTL_STSâControl/Status Register .......................................... 577
13.2.3.2 USBPIDâUSB PIDs Register ..................................................... 580
13.2.3.3 DATABUF[7:0]âData Buffer Bytes[7:0] Register ......................... 581
13.2.3.4 CONFIGâConfiguration Register ............................................... 581
14 SMBus Controller Registers (D31:F3) .................................................................... 583
14.1 PCI Configuration Registers (SMBUSâD31:F3) .................................................... 583
14.1.1 VIDâVendor Identification Register (SMBUSâD31:F3) .............................. 583
14.1.2 DIDâDevice Identification Register (SMBUSâD31:F3) .............................. 584
14.1.3 PCICMDâPCI Command Register (SMBUSâD31:F3) ................................. 584
14.1.4 PCISTSâPCI Status Register (SMBUSâD31:F3) ....................................... 585
14.1.5 RIDâRevision Identification Register (SMBUSâD31:F3) ............................ 585
14.1.6 PIâProgramming Interface Register (SMBUSâD31:F3) ............................. 586
14.1.7 SCCâSub Class Code Register (SMBUSâD31:F3) ..................................... 586
14.1.8 BCCâBase Class Code Register (SMBUSâD31:F3).................................... 586
14.1.9 SMB_BASEâSMBUS Base Address Register (SMBUSâD31:F3) ................... 586
14.1.10SVID â Subsystem Vendor Identification Register (SMBUSâD31:F2/F4) ..... 587
14.1.11SID â Subsystem Identification Register (SMBUSâD31:F2/F4) .................. 587
14.1.12INT_LNâInterrupt Line Register (SMBUSâD31:F3)................................... 587
14.1.13INT_PNâInterrupt Pin Register (SMBUSâD31:F3) .................................... 587
14.1.14HOSTCâHost Configuration Register (SMBUSâD31:F3)............................. 588
14.2 SMBus I/O Registers ........................................................................................ 588
14.2.1 HST_STSâHost Status Register (SMBUSâD31:F3) ................................... 589
14.2.2 HST_CNTâHost Control Register (SMBUSâD31:F3) .................................. 591
14.2.3 HST_CMDâHost Command Register (SMBUSâD31:F3) ............................. 593
Intel ® ICH7 Family Datasheet
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