307013-003 Datasheet, PDF (599/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SMBus Controller Registers (D31:F3)
14.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 16h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received
7:0
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)
is set to 1.
14.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
(SMBUS—D31:F3)
Register Offset: SMBASE + 17h
Default Value: 00h
Attribute:
Size:
RO
8 bits
Note:
This register is in the resume well and is reset by RSMRST#.
Bit
Description
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received
7:0
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0)
is set to 1.
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Intel ^® ICH7 Family Datasheet
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