307013-003 Datasheet, PDF (444/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.8.3.11 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 2Ch
(ACPI GPE0_BLK + 4)
Attribute:
00000000h
Size:
No
Usage:
Bits 0–7, 9, 12, 14–31 Resume,
Bits 8, 10–11, 13 RTC
R/W
32-bit
ACPI
This register is symmetrical to the General Purpose Event 0 Status Register. All the bits
in this register should be cleared to 0 based on a Power Button Override or processor
Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC sell bits
are cleared by RTCRST#.
Bit
31:16
15
14
13
Description
GPIn_EN — R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
NOTE: Mapping is as follows: bit 31 corresponds to GPIO15 ... and bit 16
corresponds to GPIO0.
Reserved
USB4_EN — R/W.
0 = Disable.
1 = Enable the setting of the USB4_STS bit to generate a wake event. The USB4_STS
bit is set anytime USB UHCI controller #4 signals a wake event. Break events are
handled via the USB interrupt.
PME_B0_EN — R/W.
0 = Disable
1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an
SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from
S5 (if entered via SLP_TYP and SLP_EN) or power failure, but not Power Button
Override. This bit defaults to 0.
NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes.
USB3_EN — R/W.
0 = Disable.
12
1 = Enable the setting of the USB3_STS bit to generate a wake event. The USB3_STS
bit is set anytime USB UHCI controller #3 signals a wake event. Break events are
handled via the USB interrupt.
PME_EN — R/W.
0 = Disable.
11
1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
PME# can be a wake event from the S1 – S4 state or from S5 (if entered via
SLP_EN, but not power button override).
10
(Desktop
Only)
ICH7DH Only:
EL_SCI_EN — R/W. In Desktop Mode with Intel Quick Resume Technology feature
enabled, this bit enables the EL_SCI_STS signal to cause an SCI (depending on the
SCI_EN bit) when it is asserted.
In Desktop Mode, when Intel Quick Resume Technology feature is disabled, this bit
will be treated as Reserved.
ICH7 and ICH7R Only:
Reserved
444
Intel ^® ICH7 Family Datasheet